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Sequential Circuits | Flip Flops

The sequential circuits are the circuits which are form in such a sequence in which their final output is depends on both present inputs as well as the present output conditions, they are the circuits which are capable of storing some bits of memory in its, like flip flops which is capable of storing 1 bit of memory in it, like registers which are capable of storing 4 bits of memory in it, etc.

In this section we study flip flop and types of flip flops.

Flip flop:

Flip flop is a memory element which is capable of storing 1 bit of binary information in it and it is used in clocked sequential circuits, it has two outputs one is normal and other is complement of first. A flip flop can maintain a binary state indefinitely as long as power is delivered to the circuit, it is also known as bistable multivibrator.

Basic flip flop or latch or 1-bit memory cell: –

A flip flop circuit can be constructed from using two NAND gates or two NOR gates.

Truth Table: –

Truth Table: –

Types of flip flop: –

1. Clocked SR flip flop: –

SR flip flop (or Set-Reset flip flop) is a simple latch combines with clock or clock pulse, the clock is nothing but the train of pulse, SR flip flop have two inputs S and R and two outputs Q and Q̅ or Qn and Q̅n or Qn+1 and Q̅n+1, the SR flip flop will be reset (0) or set (1) at any time in terms of output by changing the inputs S and R.

Circuit Diagram: –

Operation: –

When the clock is absent or low [CLK =0] then output of both the gates G3 and G4 is 1 and there is no change in the output of G1 and G2.

When the clock is present or high [CLK =1] then the output of gates G3 and G4 are the functions of the input S and R or simply depend on S and R.

1. When S=0, R=0 then the output of the gates G3 and G4 are 1 and also the output of G1 and G2 are unchanged.
2. When S=0, R=1 then the output of G3=1 & G4=0 and the output of G1 is 0 & G2 is 1. The flip flop is reset.
3. When S=1, R=0 then the output of G3=0 & G4=1 and the output of G1 is 1 & G2 is 0. The flip flop is set.
4. When S=1, R=1 then the output of G3 & G4 are 0 and the outputs of G1 & G2 try to become 1 which is not possible, there is a race and the output is undefined, and this is known as forbidden stage.

Truth Table: –

2. JK flip flop: –

JK flip flop (or Jack Kilby flip flop) is the modification of SR flip flop circuit which is modified by the Texas instruments engineer Jack Kilby in 1958 to eliminate race condition in SR flip flop, the modified flip flop is named JK in his honor.

Circuit Diagram: –

Operation: –

When the clock is absent or low [CLK =0] then output of both the gates G3 and G4 is 1 and there is no change in the output of G1 and G2.

When the clock is present or high [CLK =1] then the output of gates G3 and G4 are the functions of the input J and K or simply depend on J and K.

1. When J=0, K=0 then the output of the gates G3 and G4 are 1 and also the output of G1 and G2 are unchanged.
2. When J=0, K=1 then the output of G3=1 & G4=0 and the output of G1 is 0 & G2 is 1. The flip flop is reset.
3. When J=1, K=0 then the output of G3=0 & G4=1 and the output of G1 is 1 & G2 is 0. The flip flop is set.
4. When J=1, K=1 then the output of G3 & G4 are the function of other input or simply depends on the feedback.

Now,

• when let to be Q=0 and Q̅=1 then the output of G3 is 0 & G4 is 1 and so that outputs of Q become 1 and Q̅ become 0.
• when let to be Q=1 and Q̅=0 then the output of G3 is 1 & G4 is 0 and so that outputs of Q become 0 and Q̅ become 1.

Hence in above two conditions (a) and (b) we can see that the output is toggling or in simple language output is inverse of inputs.

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3. D flip flop: –

D flip flop (or Delay flip flop) is a flip flop having only one input and the other is the inverse input of it which is complemented by a not gate, it can be constructed by using both SR flip flop and JK flip flop at a time, its use is only for delaying (increasing time – for working of a circuit or for getting the output from a circuit) of a circuit.

Circuit Diagram: –

Truth Table: –

4. T flip flop: –

The T flip flop (or toggle flip flop or trigger flip flop) is a flip flop having a single input which act as the twice input supply for J and K inputs, it is only constructed by using JK flip flop by connecting its J and K input together, it is used to toggle or compliment a given circuit stage.

Circuit Diagram: –

Truth Table: –

5) Master Slave flip flop: –

Master slave flip flop contains 2 JK flip flops combined together with a NOT gate in the clock pulse section and in which only one of the flip flops works at a time rather Master or Slave, when any one work second is in rest position. Master-Slave flip flop is created for solving “race around” condition in JK flip flop (When CLK=1 & J=1, K=1).

Circuit Diagram: –

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